As is known, integrated electronic devices may comprise circuit parts which, although cooperating with each other, operate on different voltage levels and must therefore be supplied with power separately. Furthermore, some of these circuit parts may require different supply voltages according to the operation mode of the device of which they form part.
For example, in non-volatile memory devices (EPROM, EEPROM, flash etc.), to which reference will be made in the rest of the description, the various circuit parts (such as those for decoding, for redundancy, for programming etc.) operate at different voltages according to the operation mode of the device (reading, programming, verifying etc.) and must therefore be connected by means of circuits known as "level shifters".
A block diagram relating to the arrangement of a voltage shifter in a non-volatile memory 10 is shown in FIG. 1, in which the voltage shifter 1, connected to a first supply line 2 at voltage Vpc, is inserted between a first circuit 3 connected to a second supply line 4 placed at the supply voltage Vdd, and a second circuit 5 connected to the first supply line 2. The voltage Vpc alternatively has, according to the operation mode presented (programming, reading, verification, . . . ), the value of the supply voltage Vdd or a voltage Vpp (typically, the programming voltage) greater than Vdd. For this purpose, the first supply line 2 is connected, by means of a controlled switch 7, to the second supply line 4 or to a supply line 6 at Vpp, where the voltage Vpp may be tapped from a suitable pin or generated internally in the device with suitable charge pumps.
In a first operation mode in which the voltage Vpc is equal to the supply voltage Vdd, the shifter 1 is not required to make any level shift but solely to reproduce the input signal correctly, with minimum delay and consumption, vice-versa, in a second operation mode, in which the voltage Vpc is equal to the voltage Vpp, the shifter 1 has to generate at the output a signal whose lowest logic state is close to the reference potential of the circuit (ground) and the highest logic state is close to the voltage Vpp.
FIG. 2 shows an embodiment of a level shifter 1' of known type, having an input 9, on which it receives an input signal Si from the circuit 3 operating at the voltage Vdd, and an output 12, on which it supplies a signal So to the circuit 5 connected to the first supply line 2.
The level shifter 1' comprises an NMOS pass transistor 15 having a first terminal connected to the input 9, a second terminal connected to an intermediate node 16 and a gate terminal connected to the second supply line 4 at voltage Vdd; an inverter 17, having N input connected to the intermediate node 16, AN output connected to the output 12 and supplied at the voltage Vpc; and a pull-up transistor 19 having a gate terminal connected to the output 12, a source terminal connected to the first supply line 2 and a drain terminal connected to the intermediate node 16.
In the level shifter 1', in the first operation mode (reading, verification, . . . ), the voltage Vpc on the first supply line 2 is equal to Vdd. If the logic state of the signal Si presented at the input 9 is low, the NMOS transistor 15 is on and transmits the low logic state onto the node 16. Consequently, the inverter 17 outputs the signal So of high logic state, equal to Vpc. This signal, also presented on the gate terminal of the pull-up transistor 19, keeps the latter off
When, however, the logic state of the signal Si is high, the NMOS transistor 15 operates like a diode as it has two terminals placed at the same voltage, it thus determines a voltage drop between the input 9 and the intermediate node 16 which is equal to its threshold voltage Vth. If the supply voltage Vdd is of high value, this voltage drop does not involve problems, and the inverter 17 carries the output signal So at low logic level. In this situation, the pull-up transistor 19 is on, stabilizing a voltage on the intermediate node 16 on the value Vpc. Vice-versa, if the supply voltage Vdd is low (2.7 V for example) this voltage drop may cause problems of functionality and of speed.
In the second operation mode (voltage Vpp on the first supply line 2), the operation of the shifter is similar to that described above. In this mode there also may be problems of functionality and speed, even in a situation of standard level of supply voltage, whenever the difference between the supply voltage Vdd and the threshold voltage Vth is low, such as not to permit the triggering of the inverter 17.
Another known embodiment of the level shifter is shown in FIG. 3, in which the shifter, denoted by 1", comprises two PMOS transistors 26, 27, two NMOS transistors 28, 29 and an inverter 30; the PMOS transistor 26 has a source terminal connected to the supply line 2 at voltage Vpc, a gate terminal connected to the output 12 and a drain terminal connected to a node 32; the NMOS transistor 28 has a drain terminal connected to the node 32, a gate terminal connected to the input 9 and a source terminal connected to ground; the PMOS transistor 27 has a source terminal connected to the first supply line 2, a gate terminal connected to the node 32 and a drain terminal connected to the output 12; the NMOS transistor 29 has a source terminal connected to ground, a drain terminal connected to the output 12, and a gate terminal connected to the output of the inverter 30; the inverter 30 is connected to the second supply line 4 at voltage Vdd and has the input connected to the input 9. Both PMOS transistors 26 and 27 have the substrate connected to the source terminal.
In both modes of operation, when the level of the signal Si is high, the NMOS transistor 28 is on and on the node 32 the signal is low. Consequently, the PMOS transistor 27 is on and the signal So is high and of value equal to Vdd in the first operation mode and Vpp in the second operation mode.
Vice-versa, if the signal Si is low, the NMOS transistor 28 is off, whilst the NMOS transistor 29 is on and the output signal So is low.
In practice, the level shifter 1" functions correctly in both modes of operation, but it has low switching speed and large size, because of the large number of transistors and the complexity of the connections. This size is particularly disadvantageous when the levels of large data or address buses have to be "shifted", for which reason the solution of FIG. 3 is difficult to apply in this case.